1. Field of the Invention
This invention relates to a testing apparatus and method for testing a semiconductor device, and more particularly to a test setup for measuring a guaranteed power loss of a semiconductor module, in which the module is not required to have on-board capacitors for the power loss test.
2. Background Art
Currently, to perform power loss testing on a semiconductor module, two large capacitors must be included in the package. These have no value to the user and are only used for power loss testing. Integrated power supply manufacturers cannot guarantee a power loss on their data sheets unless they use complex test processes and on-board capacitors. FIG. 3 shows a board to be tested in which internal input capacitors “X” are needed for a power loss test. In the power loss test circuit, power loss is calculated by the formula PLOSS=(PIN+PDD)−POUT, wherein PLOSS is power loss, PIN is input power, PDD is supply power, and POUT is output power. The module shown is the iP2003 iPOWIR™ module manufactured by the applicant, the International Rectifier Corp., described in document no. PD-96922 A dated Nov. 18, 2004, available at www.irf.com.
The conventional testing arrangement uses traditional “pogo-pins” and sockets. FIG. 1 shows a known test fixture with a “pogo-pin” contact array 30 arranged in a test socket 40 on a test board 50. FIG. 2 shows the pogo-pin structure in schematic sectional form. The pins are mounted in a relatively rigid frame 32. Each pin, for example the pin 34, has a pair of plungers 34a, 34b at its two ends, which are spring-loaded so as to retract a distance d.
The module being tested is placed from above on the test socket shown in FIG. 1, where the spring-loaded pogo pins make contact with electrodes on the module to apply power and make measurements of parameters on the module. Because the pins are fixed in location with respect to their frame and to the test socket, registration between the pins and the electrodes on the module must be very precise.
The known pogo pin arrangement can generate both stray inductance and interconnection resistance (contact resistance plus conductor resistance) which can cause oscillation and power loss at the power supply input and output, causing power loss measurements to be inaccurate. Also, if the pogo pins make poor or intermittent contact with the corresponding test points on the module, voltage transients can occur when power is applied. Such transients may waste testing time, since the test cannot be completed until the transients settle down, and they may even damage the semiconductor module.
For accurate power loss testing it is important to have a low impedance supply, comprising capacitors with little or no interconnection distance. Any increase in the separation between the supply and the module supply pins will increase stray inductance in the supply circuit. This stray inductance in turn will result in voltage oscillations (dynamic variations) on the supply pins of the module which will change the power loss and can even cause failure of the module, due to transient over-voltage conditions.
Furthermore, the power-loss measurement has to be accurate. The pogo-pins form a coarse grid with a limited number of pins making contact to each of the required pads, resulting in a high contact resistance. The pins themselves also have some resistance. This total interconnection resistance between the test socket and the module, although reasonably small, can be significant, especially at high-current power-loss testing. The voltage-drop across the interconnections also increases as the current flowing through them causes heating, thereby increasing the interconnection resistance further and changing the power-loss operating point (that is, more of the input power is dissipated within the interconnections, reducing the input power to the module).
The need to eliminate such factors, and particularly to compensate for stray inductance and realize the required low supply impedance inside and at the supply pins of the module, leads to the requirement of large on-board input and output decoupling capacitors which, as mentioned above, are of no value to the customer. They are useful only to the manufacturer, who must include the capacitors in order to test the module, for example to determine a guaranteed power loss figure.